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According to the article IBM is looking into layering the transistors. Instead of having layers in the chip for just the signal traces, they will start stacking the transistors some what like a baker layers a cake.[quote]The 3D design "adds second or multiple...layers on top of what's already there," said Kathryn Guarini, IBM's lead researcher on the project. So "instead of a single layer of transistors, we have two or three or more."
This new circuit design, which is in its early stages at IBM Research, could one day lead to more powerful chips, Guarini said. By layering transistors instead of placing them side by side as is done now, Big Blue can increase the number of transistors in a chip, boosting performance.
IBM could also reduce the length of the metal interconnects used to link the transistors, Guarini said. This would enhance performance in a manner similar to a process shrink, during which chipmakers change their manufacturing processes to produce smaller features inside chips.[/quote]
This makes me wonder if they will try the obvious, like having 2 complete processor cores in the same chip, thus giving true dual processor capability in one package. This of course would require a new cpu socket to handle all the inputs and outputs of the chip/s. I would guess that they would share pinouts were ever they could.
I wonder how this would compare to Intel's "Hyperthreading" that is just now becoming available in non-Xeon P4 chips (I don't know which ones, I think the 3.Ghz will official have it). Intel's approach gives you a virtual second processor that is recognized by Win2k and WinXP. I wonder if it would work under Linux also?
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